by Jack Goho
Gideon Analytical labs received one FDN337N-channel FET for failure analysis. The Drain to source was reported shorted. Super SOTTM-3 N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild’s high cell density DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The plastic was removed to reveal the following: 1) One of the source wires to the left was fused with the silicon (excessive inrush current) 2) Near the top edge of the step oxide coverage, there is a catastrophic electrical over stress (EOS) which shorted the terminals 3) Considerable heat damage was evident on oxide layer die melting the aluminum source metal. The current was too high in this application for the FET rating. Gideon Analytical labs can save valuable time when debugging a new design and determining the failure mode. If you need failure analysis on FET or other components call Gideon.